Sr. Physical Design Engineer
Mission:
The Physical Design Engineer will be responsible for block level synthesis, place & route and sign-off.
Responsibilities & opportunities in this role:
- Responsible for block level Synthesis, Place & Route, Timing Sign-off, Physical & Electrical Sign Off, Logical Equivalence and Low-Power checks - end to end RTL 2 GDS at block level.
- Responsible for floorplanning, IP placement, timing constraints, UPF.
- Collaborate closely with the Microarchitecture/Logic Design team to optimize the design for best PPA goals.
- Work with the Infrastructure/EDA/CAD team to optimize flows and methodology. Influence tools, flows and physical design methodology with a data driven approach to optimize flows for best PPA.
- Work closely with vendor teams to achieve various milestone goals for block level physical implementation.
Ideal candidates have/are:
- BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.
- 5-8 years of meaningful industry experience and a background in block/top level physical design of high-speed processors (i.e. Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs)
- Proven track record of implementing designs through synthesis, placement, CTS, Routing, Extraction, Timing and Physical/Electrical Verification
- Good knowledge of employing best-known methods to handle/optimize DFT structures in Physical Design at Block level.
- Strong hands-on experience in implementing multi-voltage, multi-clock domain designs.
- Proficiency in different CTS methodologies, global clock design.
- Expert in implementing PD power optimization techniques and have a keen eye to look for power reduction options throughout the PD cycle.
- Strong understanding of timing constraints & analysis, power grid design, power analysis (EMIR/di/dt), ECO generation and MCMM STA.
- Deep understanding of low power format like UPF/CPF
- Experience in formal equivalency checks, Low Power Rule verification.
- Expert in industry standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX
- Strong Automation skills using scripting languages like TCL, Python, Perl etc.
Attributes of a Groqster:
- Humility - Egos are checked at the door
- Collaborative & Team Savvy - We make up the smartest person in the room, together
- Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously
- Curious & Innovative - Take a creative approach to projects, problems, and design
- Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking
If this sounds like you, we’d love to hear from you!
Compensation: At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $169,915 to $199,900, determined by your skills, qualifications, experience and internal benchmarks.
