ABOUT THE ROLE

We are seeking a Senior DFT Engineer with 5+ years of hands-on implementation experience across MBIST, BISR, Boundary Scan, and IJTAG. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug.

In this role, you will partner closely with RTL, Physical Design, and ATE teams to deliver clean DFT signoff and robust test coverage for complex SoC designs

ESSENTIAL DUTIES AND RESPONSIBILITIES

Perform hands-on DFT implementation, including:
- MBIST and BISR insertion and integration
- Boundary Scan (IEEE 1149.x) insertion
- IJTAG (IEEE 1687) insertion and connectivity
Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent
Identify, debug, and resolve DFT rule violations at both block and top levels
Run, analyze, and debug SpyGlass DFT/RTL checks, working with design teams to close violations
Generate, simulate, and debug MBIST and logic ATPG patterns
Analyze test results and drive test coverage improvement and closure
Develop and validate DFT timing constraints for scan, BIST, and test modes
Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows
Support hierarchical DFT implementation and resolve integration issues
Collaborate with RTL and Physical Design teams to address DFT-related design issues
Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and debug as needed

QUALIFICATIONS

Bachelor’s degree with 6+ years of relevant experience, or Master’s degree with 5+ years of relevant experience
5+ years of hands-on DFT implementation experience
Strong proficiency with Siemens Tessent, including:
- MBIST / BISR insertion and verification
- Boundary Scan (IEEE 1149.x)
- IJTAG (IEEE 1687)
- ATPG pattern generation and coverage analysis
Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
Strong TCL scripting skills for DFT automation and flow execution
Experience developing and validating scan and test-mode timing constraints
End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug
Strong debugging skills, attention to detail, and sense of ownership
Excellent verbal and written communication skills

PREFERRED QUALIFICATIONS

Experience driving MBIST coverage improvement and repair efficiency optimization
Post-silicon experience, including:
- Pattern bring-up and debug
- Tester pattern conversion
- Silicon characterization
Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing

LOCATION: Santa Clara, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $200,000.00 - $220,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.

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