ABOUT THE ROLE
Celestial AI is looking for a Verification & Emulation Methodology Engineer who thrives on both building methodology and using it daily. In this role you will:
- Contribute directly to block- and system-level verification in SystemVerilog/UVM, driving coverage and closing bugs.
- Build and scale the automation and infrastructure that enables the entire team to be more effective.
Because we are a startup, you will split your time between hands-on DV work (tests, debug, coverage closure) and methodology development (regressions, dashboards, CI, emulation flows). We believe the best methodology is created by those who actively use it.
This is a rare opportunity to both shape modern verification infrastructure and apply it on cutting-edge photonic AI hardware with minimal legacy constraints.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Regression Platform: Design, maintain, and scale end-to-end regression infrastructure while also running hands-on regressions for your verification tasks.
- Coverage Methodology: Develop and apply robust coverage flows, ensuring meaningful analytics and closure.
- Emulation Flow Development: Create and use emulation flows for HW/SW co-verification, performance validation, and debug acceleration.
- Dashboards & Insights: Build visualization and alerts to track regressions and coverage.
- Cross-Functional Partnership: Work closely with design and DV teams to codify best practices, debug efficiently, and perform root-cause analysis; collaborate with platform/IT teams operating CI and the compute farm.
- Innovation & Evaluation: Pilot new tools and techniques to improve performance, observability, cost, and throughput, while grounding proposals in your own verification experience.
QUALIFICATIONS
- Bachelor’s in Computer/Electrical Engineering, Computer Science, or related field and 5+ years of experience; or Master’s and 3+ years of experience.
- Proven background in verification or EDA methodology development for ASIC/SoC programs.
- Strong scripting/software skills: Python and Linux shell required; Comfortable with packaging, testing, and code quality for internal tools.
- Familiarity with industry simulators and emulators (e.g., Cadence Xcelium, Synopsys VCS, Siemens Questa; and emulation platforms such as Palladium/Protium, ZeBu, or Veloce).
- Working knowledge of SystemVerilog/UVM concepts sufficient to instrument flows and reason about coverage/testbench structure (deep DV expertise a plus).
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
