ABOUT THE ROLE
We are seeking a highly skilled and experienced timing and Synthesis Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, synthesis, front-end implementation flows & methodologies for both SOC level and block level. They should have experience that includes logic synthesis (MMMC synthesis), logic equivalency checks, STA, timing constraints, functional ECOs, hard IP integration, timing budgeting, optimization, and timing closure of high-speed designs. Experience with deep technology nodes such as 5nm/4nm is highly valued.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Develop and validate timing constraints for intricate SoC designs
- Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows
- Own and contribute to various Front-End Implementation tasks & flows such as Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc.
- Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
- Perform static timing analysis (STA) using industry-standard tools (e.g., Tempus, Primetime)
- Define and implement Synthesis & timing signoff methodologies, including process corners, derates, and uncertainties
- Resolve tool issues, independently or working with EDA tool vendors
- Conduct pre-route timing checks and quality of results (QoR) analysis
- Automate front end flows and timing analysis processes using scripting languages such as Tcl or Python
- Create QoR dashboards, histograms for Synthesis & STA flows
- Ensure compliance with timing signoff checklists and criteria
- Document best practices and lessons learned to drive continuous improvements in future projects
QUALIFICATIONS
- Bachelor's degree in electrical or computer engineering (advanced degree preferred)
- Minimum of 5 years of industry experience in ASIC implementation, STA and synthesis
- Strong understanding of ASIC design flows, from RTL to GDSII
- Knowledge and hands-on experience with synthesis & STA methodologies and implementation
- Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Python)
- Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5
- Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff
- Familiarity with physical design and timing optimization techniques and strategies to achieve physical design and timing closure
- Proven track record of delivering successful designs on time and meeting performance, power and area goals
- Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues
- Strong communication and collaboration skills to work effectively within cross-functional teams.
PREFERRED QUALIFICATIONS
- Master's degree in electrical engineering or computer engineering
- A minimum of 5+ years of hands-on experience in ASIC Synthesis, timing constraints development, STA & timing closure with Cadence or Synopsys tools.
- Knowledge of hierarchical physical design flows, for large chips.
LOCATION: Orange County, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $220,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
