ABOUT THE ROLE
We are seeking an experienced Verification Engineer with strong expertise in SystemVerilog and UVM methodologies to join our collaborative team. You will play a key role in defining verification strategies, developing robust UVM environments, and enhancing our overall verification infrastructure. Our team works on complex IP and SoC verification, including emulation, AMS Co-Simulation, and industry-leading UVM methodologies.
ESSENTIAL DUTIES AND RESPONSIBILITIES
QUALIFICATIONS
- Bachelor's degree in electrical engineering or related discipline with at least 4+ years of relevant experience; Master's degree preferred.
- Strong proficiency in SystemVerilog and deep expertise in UVM methodology, including constrained random testing techniques.
- Solid scripting skills, particularly in Python, to automate verification tasks and infrastructure.
- Proven track record achieving thorough functional and code coverage, demonstrating high-quality verification outcomes.
- Excellent communication skills, with the ability to effectively collaborate across diverse technical teams.
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $200,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
