ABOUT THE ROLE
We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.
This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Lead a team of high performing ASIC design engineers responsible for RTL design of IPs, subsystems and SOCs supporting Celestial AI’s photonic fabric roadmap.
- Develop project schedules, define milestones, allocate resources, manage budgets and ensure timely delivery of high-quality designs that meet product functional and performance goals.
- Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
- Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
- Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
- Mentor the team, foster a culture of continuous learning and actively help with career development.
- Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in timely fashion to support team deliverables.
QUALIFICATIONS
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 8+ years of ASIC/SOC digital design experience and 3+ years of people management experience.
- Excellent leadership, communication, team building and stakeholder management skills.
- Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
- Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
- Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
- Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc.
- Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
- Proficiency with front end development tools/methodologies, and scripting for automation and flow integration.
PREFERRED QUALIFICATIONS
- PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience managing relationships with external design partners, IP vendors, and foundries.
- Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $205,000.00 - $235,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
